1. Field of the Invention
The present invention relates generally to a peak holding circuit, and more particularly, to a peak holding circuit formed as an integrated circuit to be employed in a color television receiver such as a liquid crystal color television receiver.
2. Description of the Prior Art
In general, if a capacitance is formed in an integrated circuit (IC), the capacitance value thereof is restricted to several 10 pF or less due to various restrictions in integrated circuit fabrication. Therefore, when a large capacitance is required, a capacitor is in general externally connected to the integrated circuit. As one example of such external connection, it is known that a holding capacitor in a peak holding circuit employed as an automatic chroma control circuit (ACC circuit) or the like in a chrominance signal reproducing circuit in a color television receiver is externally connected to an integrated circuit, which is disclosed in, for example, Japanese Patent Publication No. 14072/1982.
However, a method is proposed for forming a capacitor in an integrated circuit without making such external connection.
FIG. 1 is a block diagram showing schematically a structure of a color television receiver including an ACC circuit adapted such that a capacitor is formed in an integrated circuit as described above.
In FIG. 1, a color television signal is received by a receiving antenna 1 and a tuner 2, from which a video signal is further extracted by a detector circuit 3. The extracted video signal is applied to a video amplifier circuit 4, to be amplified. An output of the video amplifier circuit 4 is applied to a band pass amplifier circuit 5 and a color output circuit 6. The band pass amplifier circuit 5 extracts a carrier chrominance signal and a color burst from the applied video signal, and applies the carrier chrominance signal to a color demodulator circuit 7 and applies a composite chrominance signal comprising the carrier chrominance signal and the color burst to a burst gate circuit 8. The burst gate circuit 8 is responsive to a burst gate pulse generated by a well-known synchronizing separator circuit (not shown) and a burst gate pulse generating circuit (not shown) for extracting the color burst from the received composite chrominance signal and applying the same to an ACC circuit 9 and a color synchronizing circuit 10. The color synchronizing circuit 10 generates a color subcarrier which is synchronized with the applied color burst and applies the same to the color demodulator circuit 7.
The color demodulator circuit 7 extracts a color difference signal from the carrier chrominance signal using this color subcarrier and applies the same to the color output circuit 6. A color picture tube 11 is driven in response to an output signal of the color output circuit 6.
On the other hand, the ACC circuit 9 automatically adjusts the gain of the band pass amplifier circuit 5 such that a level of the carrier chrominance signal applied to the color demodulator circuit 7 from the band pass amplifier circuit 5 is kept constant. More specifically, the ACC circuit 9 is adapted to detect the magnitude of the color burst extracted by the burst gate circuit 8 and to decrease the gain of the band pass amplifier circuit 5 if the color burst becomes large to keep constant the level difference between a luminance signal and the carrier chrominance signal such that the depth of color of a picture becomes constant.
More specifically, the color burst applied to the ACC circuit 9 from the burst gate circuit 8 is first applied to a well-known ACC detector circuit 9a structured by a double-balanced differential amplifier. This ACC detector circuit 9a demodulates the applied color burst and applies a detected output to a base of a transistor Q.sub.1. The transistor Q.sub.1 is responsive to this detected output to be turned on only in a burst period. A peak holding capacitor C.sub.1 is connected between an emitter of the transistor Q.sub.1 and a ground potential. In the burst period, signal charges corresponding to a peak value of the color burst are charged in this capacitor C.sub.1 through the transistor Q.sub.1. In addition, there are provided transistors Q.sub.2, Q.sub.3 and Q.sub.4 connected in a triple darlington manner. The transistor Q.sub.2 has its base connected to the emitter of the transistor Q.sub.1 and one electrode of the capacitor C.sub.1. Furthermore, an emitter output of the transistor Q.sub.4 is applied to a variable gain control type ACC amplifier circuit 9b as well as to a collector of a transistor Q.sub.5 serving as a constant current source.
In the above described ACC circuit 9, the input impedance of a darlington circuit comprising the transistors Q.sub.2 to Q.sub.4 is large, so that a sufficient emitter output of the transistor Q.sub.4 can be obtained by only supplying a small amount of current. In other words, even if the capacitance value of the capacitor C.sub.1 is decreased (specifically, several 10 pF or less), the driving capability is sufficient. As a result, the peak holding capacitor C.sub.1 can be formed in the integrated circuit.
However, the ACC circuit 9 shown in FIG. 1 has the following two disadvantages.
The first disadvantage is that since a collector cut-off current flowing through the transistor Q.sub.2 in the first stage out of the transistors connected in a darlington manner, i.e., a current flowing between a collector and an emitter of the transistor when a base and the emitter thereof are short-circuited through a resistor is amplified by the transistors Q.sub.3 and Q.sub.4 in the succeeding stages, more current than necessary flows through the transistor Q.sub.4 in the final stage even if the transistor Q.sub.2 in the first stage is off.
More specifically, assuming that current amplification factors of the transistors Q.sub.2, Q.sub.3 and Q.sub.4 are respectively B.sub.1, B.sub.2 and B.sub.3, collector cut-off currents thereof are respectively I.sub.CER1, I.sub.CER2 and I.sub.CER3, and a current flowing through the transistor Q.sub.4 in the final stage is IF, we obtain: EQU IF=(I.sub.CER1 .times.B.sub.2 +I.sub.CER2).times.B.sub.3 +I.sub.CER3 EQU where EQU I.sub.CER1 .multidot.B.sub.2 &gt;&gt;I.sub.CER2 EQU I.sub.CER1 .multidot.B.sub.2 .multidot.B.sub.3 &gt;&gt;I.sub.CER3 EQU and thus EQU IF.apprxeq.I.sub.CER2 .multidot.B.sub.2 .multidot.B.sub.3
If concrete numerical values are substituted to calculate the above described IF, we obtain: EQU IF.apprxeq.0.01.mu.A.times.300.times.300=0.9mA
Thus, if such a current IF flows, an output potential of the transistor Q.sub.4 is unnecessarily raised in a period other than the burst period, i.e., in an off period of the transistor Q.sub.2, so that the ACC circuit can not perform a normal operation. In order to control such rise in output potential, a reactive current I.sub.0 larger than the above described current IF, for example, approximately 1 mA must be allowed to flow through the transistor Q.sub.5 serving as a constant current source. Thus, a method has been known for compensating for an unnecessary change in potential at the time of no signal by a transistor separately provided, which is disclosed in, for example, Japanese Patent Publication No. 42242/1982.
However, if a constant current source is provided such that a reactive current of 1 mA is always allowed to flow as described above, power consumption is increased.
The second disadvantage is that ripple occurs in a voltage held in the peak holding capacitor C.sub.1. FIG. 2 is a diagram showing the change with time of a voltage held in the holding capacitor C.sub.1 shown in FIG. 1. Referring now to FIG. 2, description is made on occurrence of ripple.
First, the transistor Q.sub.1 is turned on in the burst period (the period of t.sub.0 to t.sub.1 shown in FIG. 2) as described above, during which charges Q.sub.H are stored in the capacitor C.sub.1 by a voltage V.sub.0. After the burst period is elapsed so that the transistor Q.sub.1 is turned off, i.e., after t.sub.1, the holding capacitor C.sub.1 attempts to hold the stored charges Q.sub.H.
However, in general, a capacitance C.sub.S0 between a base and an emitter and a capacitance C.sub.S1 between a collector and a base exist in a transistor. Thus, when the transistor Q.sub.1 is rendered non-conductive so that one end on the side of a base of a capacitance C.sub.S0 between a base and an emitter of the transistor Q.sub.1 becomes a ground potential, the above described charges Q.sub.H are divided into a capacitance C.sub.1 of the capacitor C.sub.1 and the capacitance C.sub.S0 between the base and the emitter, as expressed in the following equation: ##EQU1## from this equation, we obtain: ##EQU2##
Thus, this .DELTA.V corresponds to the amount of decrease in voltage held in the holding capacitor C.sub.1 after t.sub.1, as shown in FIG. 2, which becomes ripple.
If the holding capacitor is externally connected to the integrated circuit and the capacitance thereof is relatively large, we obtain: EQU C.sub.1 &gt;C.sub.S0
and thus .DELTA.V is extremely small, so that little ripple occurs. However, if the peak holding capacitor C.sub.1 is formed in the integrated circuit as a small capacitance of several 10 pF or less as described above, .DELTA.V becomes large, so that ripple occurs, whereby a correct peak holding operation cannot be performed.